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<A name="Par"></A>Copyright (c) 2002-2022 Lattice Semiconductor Corporation,  All rights reserved.

Thu Mar 16 11:17:31 2023

Command Line: par -w -n 1 -t 1 -s 1 -cores 1 -exp parPathBased=ON \
	awg_fpga_impl_1_map.udb awg_fpga_impl_1.udb 


<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
Level/       Number       Worst        Timing       Worst        Timing       Run          Run
Cost [udb]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
----------   --------     -----        ------       -----------  -----------  ----         ------
5_1   *      0            -            -            -            -            05           Completed
* : Design saved.

Total (real) run time for 1-seed: 5 secs 

par done!

Lattice Place and Route Report for Design &quot;awg_fpga_impl_1_map.udb&quot;
Thu Mar 16 11:17:31 2023


<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
PAR: Place And Route Radiant Software (64-bit) 2022.1.0.52.3.
Command Line: par -w -t 1 -cores 1 -exp parPathBased=ON awg_fpga_impl_1_map.udb \
	awg_fpga_impl_1_par.dir/5_1.udb 

Loading awg_fpga_impl_1_map.udb ...
Loading device for application GENERIC from file &apos;itpa08.nph&apos; in environment: C:/lscc/radiant/2022.1/ispfpga.
Package Status:                     Preliminary    Version 1.5.
Performance Hardware Data Status:   Advanced       Version 1.0.



Design:  awg
Family:  iCE40UP
Device:  iCE40UP5K
Package: SG48
Performance Grade:   High-Performance_1.2V
Number of Signals: 928
Number of Connections: 2066

<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>

   SLICE (est.)     243/2640          9% used
     LUT            454/5280          8% used
     REG            201/5280          3% used
   PIO               16/56           28% used
                     16/36           44% bonded
   IOLOGIC            0/56            0% used
   DSP                5/8            62% used
   I2C                0/2             0% used
   HFOSC              0/1             0% used
   LFOSC              0/1             0% used
   LEDDA_IP           0/1             0% used
   RGBA_DRV           0/1             0% used
   FILTER             0/2             0% used
   SRAM               0/4             0% used
   WARMBOOT           0/1             0% used
   SPI                0/2             0% used
   EBR               10/30           33% used
   PLL                0/1             0% used
   RGBOUTBUF          0/3             0% used
   I3C                0/2             0% used
   OPENDRAIN          0/3             0% used

Pin Constraint Summary:
   16 out of 16 pins locked (100% locked).

Finished Placer Phase 0 (HIER). CPU time: 0 secs , REAL time: 0 secs 


................
Finished Placer Phase 0 (AP).  CPU time: 0 secs , REAL time: 0 secs 

Starting Placer Phase 1. CPU time: 0 secs , REAL time: 0 secs 
..  ..
....................

Placer score = 129207.

Device SLICE utilization summary after final SLICE packing:
   SLICE            239/2640          9% used

Finished Placer Phase 1. CPU time: 3 secs , REAL time: 4 secs 

Starting Placer Phase 2.
.

Placer score =  278897
Finished Placer Phase 2.  CPU time: 3 secs , REAL time: 4 secs 



<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>

Global Clocks :
  PRIMARY &quot;clk_c&quot; from comp &quot;clk&quot; on CLK_PIN site &quot;44 (PL7B)&quot;, clk load = 129, ce load = 0, sr load = 0
  PRIMARY &quot;rst_n_N_209&quot; from F0 on comp &quot;U3.SLICE_339&quot; on site &quot;R13C31D&quot;, clk load = 0, ce load = 0, sr load = 95

  PRIMARY  : 2 out of 8 (25%)




I/O Usage Summary (final):
   16 out of 56 (28.6%) I/O sites used.
   16 out of 36 (44.4%) bonded I/O sites used.
   Number of I/O components: 16; differential: 0
   Number of Vref pins used: 0

I/O Bank Usage Summary:
+----------+---------------+------------+------------+------------+
| I/O Bank | Usage         | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+---------------+------------+------------+------------+
| 0        | 2 / 14 ( 14%) | 3.3V       |            |            |
| 1        | 9 / 14 ( 64%) | 3.3V       |            |            |
| 2        | 5 / 8 ( 62%)  | 3.3V       |            |            |
+----------+---------------+------------+------------+------------+

Total Placer CPU time: 3 secs , REAL time: 4 secs 

Writing design to file awg_fpga_impl_1_par.dir/5_1.udb ...


-----------------------------------------------------------------
INFO - par: ASE feature is off due to non timing-driven settings.  
-----------------------------------------------------------------


Start NBR router at 11:17:35 03/16/23

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in timing report. You should always run the timing    
      tool to verify your design.                                
*****************************************************************

Starting routing resource preassignment
Preassignment Summary:
--------------------------------------------------------------------------------
397 connections routed with dedicated routing resources
2 global clock signals routed
621 connections routed (of 1929 total) (32.19%)
---------------------------------------------------------
Clock routing summary:
Primary clocks (2 used out of 8 available):
#1  Signal &quot;clk_c&quot;
       Clock   loads: 129   out of   129 routed (100.00%)
       Data    loads: 0     out of     1 routed (  0.00%)
#4  Signal &quot;rst_n_N_209&quot;
       Control loads: 95    out of    95 routed (100.00%)
---------------------------------------------------------
--------------------------------------------------------------------------------
Completed routing resource preassignment

Start NBR section for initial routing at 11:17:35 03/16/23
Level 4, iteration 1
32(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 

Info: Initial congestion level at 75.00% usage is 0
Info: Initial congestion area  at 75.00% usage is 0 (0.00%)

Start NBR section for normal routing at 11:17:35 03/16/23
Level 4, iteration 1
8(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 
Level 4, iteration 2
4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 
Level 4, iteration 3
3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 
Level 4, iteration 4
3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 
Level 4, iteration 5
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 
Level 4, iteration 6
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 
Level 4, iteration 7
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 
Level 4, iteration 8
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 
Level 4, iteration 9
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 
Level 4, iteration 10
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 
Level 4, iteration 11
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 

Start NBR section for post-routing at 11:17:36 03/16/23

End NBR router with 0 unrouted connection


<A name="par_nbrsum"></A><B><U><big>NBR Summary</big></U></B>
-----------
  Number of unrouted connections : 0 (0.00%)
-----------


Total CPU time 0 secs 
Total REAL time: 0 secs 
Completely routed.
End of route.  1929 routed (100.00%); 0 unrouted.

Writing design to file awg_fpga_impl_1_par.dir/5_1.udb ...


All signals are completely routed.


PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack&lt;setup/&lt;ns&gt;&gt; = &lt;n/a&gt;
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = &lt;n/a&gt;
PAR_SUMMARY::Worst  slack&lt;hold /&lt;ns&gt;&gt; = &lt;n/a&gt;
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = &lt;n/a&gt;
PAR_SUMMARY::Number of errors = 0

Total CPU  Time: 4 secs 
Total REAL Time: 5 secs 
Peak Memory Usage: 87.61 MB


par done!

Note: user must run &apos;timing&apos; for timing closure signoff.

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2022 Lattice Semiconductor Corporation,  All rights reserved.



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<DIV id="toc" class="radiant"><span onmousemove="showTocList()">Contents</span>
<UL id="toc_list">
<LI><A href=#par_cts>Cost Table Summary</A></LI>
<LI><A href=#par_best>Best Par Run</A></LI>
<LI><A href=#par_dus>Device utilization summary</A></LI>
<LI><A href=#par_clk>Clock Report</A></LI>
<LI><A href=#par_nbrsum>NBR Summary</A></LI>
</UL>
</DIV>

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